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| Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS FEATURES n n CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS General Description The CDK8307 is a high performance low power octal analog-to-digital converter (ADC). The ADC employs internal reference circuitry, a serial control interface and serial LVDS output data, and is based on a proprietary structure. An integrated PLL multiplies the input sampling clock by a factor of 12 or 14, according to the LVDS output setting. The multiplied clock is used for data serialization and data output. Data and frame synchronization output clocks are supplied for data capture at the receiver. Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determines the exact function of this external pin. The CDK8307 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. The very low startup times of the CDK8307 allow significant power reduction in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when the receive path is idle. 20/40/50/65/80MSPS max sampling rate Low Power Dissipation - 23mW/channel at 20MSPS - 35mW/channel at 40MSPS - 41mW/channel at 50MSPS - 51mW/channel at 65MSPS - 59mW/channel at 80MSPS 72.2dB SNR at 8MHz FIN 0.5s startup time from Sleep 15s startup time from Power Down Internal reference circuitry requires no external components Internal offset correction Reduced power dissipation modes available - 34mW/channel at 50MSPS - 71.5dB SNR at 8MHz FIN Coarse and fine gain control 1.8V supply voltage Serial LVDS output - 12- and 14-bit output available n n n n n n n n n Block Diagram RESETN SCLK SDATA AVDD AVSS DVDD DVSS LVDS FCLKP FCLKN LCLKP LCLKN D1N D1P D2N D2P LVDS LVDS CLKP CLKN CSN PD PLL Digital Gain Digital Gain n Package alternatives - TQFP-80 - QFN-64 APPLICATIONS n n n n Medical Imaging Wireless Infrastructure Test and Measurement Instrumentation IP2 IN2 IP1 IN1 Serial Control Interface ADC Clock Input ADC * * * IP8 IN8 ADC * * * Digital Gain * * * LVDS D8N D8P Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Table of Contents Features .................................................................. 1 Applications ............................................................ 1 General Description ................................................ 1 Block Diagram ........................................................ 1 Table of Contents ................................................... 2 Ordering Information ............................................. 3 Pin Configurations .................................................. 4 Pin Assignments .................................................. 5-8 Absolute Maximum Ratings ................................... 9 Reliability Information ........................................... 9 ESD Protection ........................................................ 9 Recommended Operating Conditions .................... 9 Electrical Characteristics...................................... 10 Electrical Characteristics - CDK8307A ............10-11 Electrical Characteristics - CDK8307B ................ 11 Electrical Characteristics - CDK8307C ............11-12 Electrical Characteristics - CDK8307D............12-13 Electrical Characteristics - CDK8307E ................ 13 Digital and Timing Electrical Characteristics ..13-14 LVDS Timing Diagrams ......................................... 15 Figure 1. 12-bit Output, DDR Mode......................... 15 Figure 2. 14-bit Output, DDR Mode......................... 15 Figure 3. 12-bit Output, SDR Mode ......................... 15 Figure 4. Data Timing ............................................ 15 Serial Interface ..................................................... 16 Timing Diagram .................................................... 16 Figure 5. Serial Port Interface Timing Diagram ..... 16 Table 1. Serial Port Interface Timing Definitions ... 16 Register Initialization ............................................. 16 Serial Register Map ..........................................17-18 Table 2. Summary of Functions Supported by Serial Interface ................................17-18 Description of Serial Registers ........................18-25 Table 3. Software Reset ......................................... 18 Table 4. Power-Down Modes .................................. 18 Table 5. LVDS Drive Strength Programmability ......... 19 Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data ............................... 19 Table 7. LVDS Internal Termination Programmability ....................................... 20 Table 8. LVDS Output Internal Termination .............. 20 Table 9. Analog Input Invert................................... 20 Table 10. LVDS Test Patterns .................................. 21 Table 11. Programmable Gain................................. 21 Table 12. Gain Setting for Channels 1-8 .................. 22 Table 13. LVDS Clock Programmability and Data Output Modes ................................. 22 Figure 6. Phase Programmability Modes for LCLK ..... 23 Figure 7. SDR Interface Modes ............................... 23 Table 14. Number of Serial Output Bits ................... 23 Figure 8. LVDS Output Timing Adjustment .............. 24 Table 15. Full Scale Control .................................... 24 Table 16. Register Values with Corresponding Charge in Full-Scale Range ...................... 25 Table 17. Clock Frequency ...................................... 25 Table 18. Clock Frequency Settings ......................... 25 Table 19. Performance Control................................ 25 Table 20. Performance Control Settings ................... 26 Table 21. External Common Mode Voltage Buffer Driving Strength ........................... 26 Theory of Operation ............................................. 27 Recommended Usage ........................................... 27 Analog Input ......................................................... 27 Figure 9. Input Configuration Diagram ................ 27 DC-Coupling.......................................................... 27 Figure 10. DC-Coupled Input .............................. 27 AC-Coupling .......................................................... 28 Figure 11. Transformer Coupled Input ................. 28 Figure 12. AC-Coupled Input .............................. 28 Figure 13. Alternative Input Network................... 28 Clock Input and Jitter Considerations ...................... 29 Mechanical Dimensions ...................................30-31 QFN-64 Package.................................................... 30 TQFP-80 Package .................................................. 31 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Ordering Information Part Number CDK8307AITQ80 CDK8307AILP64 CDK8307BITQ80 CDK8307BILP64 CDK8307CITQ80 CDK8307CILP64 CDK8307DITQ80 CDK8307DILP64 CDK8307EITQ80 CDK8307EILP64 Speed 20MSPS 20MSPS 40MSPS 40MSPS 50MSPS 50MSPS 65MSPS 65MSPS 80MSPS 80MSPS Package TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 TQFP-80 QFN-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Packaging Method Tray Tray CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Tray Tray Tray Tray Tray Tray Tray Tray Moisture sensitivity level for QFN package is MSL-2A, for TQFP package is MSL-3. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Pin Configurations QFN-64 RESETN SDATA OVDD AVDD AVDD TP AVSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD CLKN SCLK CLKP VCM CSN NC NC NC NC CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS IP1 IN1 AVSS IP2 IN2 AVSS IP3 IN3 AVSS IP4 IN4 DVSS PD DVSS D1P D1N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 17 18 19 20 21 22 23 24 25 26 27 28 29 32 48 47 46 45 44 IN8 IP8 AVSS IN7 IP7 AVSS IN6 IP6 AVSS IN5 IP5 AVSS DVSS DVDD D8N D8P CDK8307 QFN-64 43 42 41 40 39 38 37 36 35 34 33 FCLKP D2P D3P D4P D5P D6P FCLKN LCLKP D2N D3N D4N D5N D6N D7P OVDD AVDD AVDD CLKN SCLK CLKP AVSS AVSS AVSS AVSS AVSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 AVDD IP1 IN1 AVSS IP2 IN2 AVDD AVSS IP3 IN3 AVSS IP4 IN4 AVDD DVSS PD DVSS DVSS LCLKP LCLKN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 TP AVSS VCM CSN NC NC NC NC NC TQFP-80 SDATA LCLKN D7N 60 59 58 57 56 55 54 AVDD IN8 IP8 AVSS IN7 IP7 AVDD AVSS IN6 IP6 AVSS IN5 IP5 AVDD DVSS RESETN DVSS DVSS FCLKN FCLKP CDK8307 TQFP-80 53 52 51 50 49 48 47 46 45 44 43 42 41 33 34 35 37 38 39 21 22 23 24 25 26 27 28 29 30 31 32 36 40 Rev 1A D1P D2P D3P D4P D5P D6P D7P DVSS DVSS D1N D2N D3N D4N D5N D6N D7N D8P DVDD DVDD D8N (c)2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Pin Assignments - QFN Pin No. QFN-64 49, 50, 57 3, 6, 9, 37, 40, 43, 46 1 2 4 5 7 8 10 11 38 39 41 42 44 45 47 48 12, 14, 36 35 13 15 16 17 18 19 20 21 22 27 28 29 30 31 32 33 34 23 24 25 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N FCLKP FCLKN LCLKP Analog power supply, 1.8V Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature. LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output LVDS bit clock, positive output Pin Name Description CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Pin Assignments QFN (Continued) Pin No. 26 51, 54, 55, 56 52 53 58 59 60 61 62 63 64 Pin Name LCLKN NC TP VCM CLKP CLKN OVDD CSN SDATA SCLK RESETN Description LVDS bit clock, negative output Not connected Test pin. Leave open (un-connected) or connect to GND. Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input Reset SPI interface CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Pin Assignments - TQFP Pin No. TQFP 1, 7, 14, 47, 54, 60, 63, 70 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 2 3 5 6 9 10 12 13 48 49 51 52 55 56 58 59 15, 17, 18, 26, 36, 43, 44, 46 25, 35 16 19 20 21 22 23 24 27 28 29 30 31 32 33 34 37 38 39 40 AVDD AVSS IP1 IN1 IP2 IN2 IP3 IN3 IP4 IN4 IP5 IN5 IP6 IN6 IP7 IN7 IP8 IN8 DVSS DVDD PD LCKP LCKN D1P D1N D2P D2N D3P D3N D4P D4N D5P D5N D6P D6N D7P D7N D8P D8N Analog power supply, 1.8V Pin Name Description CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Analog ground Positive differential input signal, channel 1 Negative differential input signal, channel 1 Positive differential input signal, channel 2 Negative differential input signal, channel 2 Positive differential input signal, channel 3 Negative differential input signal, channel 3 Positive differential input signal, channel 4 Negative differential input signal, channel 4 Positive differential input signal, channel 5 Negative differential input signal, channel 5 Positive differential input signal, channel 6 Negative differential input signal, channel 6 Positive differential input signal, channel 7 Negative differential input signal, channel 7 Positive differential input signal, channel 8 Negative differential input signal, channel 8 Digital ground Digital and I/O power supply, 1.8V Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature. LVDS bit clock, positive output LVDS bit clock, negative output LVDS channel 1, positive output LVDS channel 1, negative output LVDS channel 2, positive output LVDS channel 2, negative output LVDS channel 3, positive output LVDS channel 3, negative output LVDS channel 4, positive output LVDS channel 4, negative output LVDS channel 5, positive output LVDS channel 5, negative output LVDS channel 6, positive output LVDS channel 6, negative output LVDS channel 7, positive output LVDS channel 7, negative output LVDS channel 8, positive output LVDS channel 8, negative output Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet Pin Assignments - TQFP (Continued) Pin No. 41 42 45 61 62, 64, 66, 67, 69 65 71 72 75 76 77 78 Pin Name FCLKP FCLKN RESETN TP NC VCM CLKP CLKN OVDD CSN SDATA SCLK Description LVDS frame clock (1x), positive output LVDS frame clock (1x), negative output Reset SPI interface Test pin. Leave open (un-connected) or connect to GND. Not connected Common mode output pin, 0.5 AVDD Positive differential input clock Negative differential input clock. Digital CMOS inputs supply voltage (1.7V to 3.6V) Chip select enable. Active low. Serial data input Serial clock input CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Parameter AVDD DVDD OVDD AVSS, DVSS Analog inputs and outpts (IPx, INx) CLKx LVDS outputs Digital inputs Reference Pin AVSS DVSS AVSS DVSS / AVSS AVSS AVSS DVSS DVSS Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +2.3 +2.3 +3.9 +0.3 +2.3 +3.9 +2.3 +3.9 Unit V V V V V V V V Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max TBD +150 Unit C C ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) QFN-64 2kV 500V Recommended Operating Conditions Parameter Operating Temperature Range Min -40 Typ Max +85 Unit C This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range from device failure to performance degradation. Analog circuitry may be more susceptible to damage as vary small parametric changes can result in specification noncompliance. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol DC Accuracy Parameter No Missing Codes Offset Error Gain Error Gain Matching Conditions Min Typ Guaranteed Max Units CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Offset error after digital offset cancellation 1 6 LSB %FS %FS LSB LSB V VCM +0.2 V Vpp pF MHz Gain matching between channels. 3sigma value at worst case conditions. 12-bit level 12-bit level 0.5 0.2 0.6 VAVDD/2 DNL INL VCMO Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth Analog Input VCMI VFSR Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth 500 1.7 Digital and output driver supply voltage Digital and output driver supply voltage 1.7 1.8 1.7 1.8 1.8 1.9 1.8 2.0 2.0 2.0 3.6 VCM -0.1 2.0 2 Power Supply AVDD DVDD OVDD Analog Supply Voltage Digital Supply Voltage (up to 65MSPS) Digital Supply Voltage (above 65MSPS) Digital CMOS Input Supply Voltage V V V V Electrical Characteristics - CDK8307A (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 47 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW W mW Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Power down mode Deep sleep mode Digital and output driver supply 54 84 97 180 10 30 Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet Symbol Parameter Sleep Channel Mode Dissipation Sleep Channel Mode Savings Conditions All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off Min Typ 46 17 Max Units mW mW MSPS Clock Inputs Maximum Conversion Rate Minimum Conversion Rate 20 15 MSPS CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Electrical Characteristics - CDK8307B (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 90 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW W mW mW mW MSPS Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 40 20 Digital and output driver supply 67 162 120 280 10 41 71 26 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Electrical Characteristics - CDK8307C (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz Min 70 69 Typ 72.2 71.5 71.5 70.7 Max Units dBFS dBFS dBFS dBFS Rev 1A Signal to Noise Ratio Signal to Noise and Distortion Ratio (c)2009 CADEKA Microcircuits LLC www.cadeka.com 11 Data Sheet Symbol SFDR HD2 HD3 ENOB Crosstalk Parameter Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 75 85 75 Typ 82 77 95 95 82 77 11.6 11.5 95 111 Max Units dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW W mW mW mW MSPS CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 50 20 Digital and output driver supply 73 200 132 331 10 46 83 31 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Electrical Characteristics - CDK8307D (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 70 69 75 85 75 Typ 72.2 71.5 71.5 70.7 82 77 95 95 82 77 11.6 11.5 95 143 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW W mW mW Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation (c)2009 CADEKA Microcircuits LLC Digital and output driver supply 83 257 149 405 Rev 1A Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) 10 54 103 www.cadeka.com 12 Data Sheet Symbol Clock Inputs Maximum Conversion Rate Minimum Conversion Rate 65 20 MSPS MSPS Parameter Sleep Channel Mode Savings Conditions Power dissipation savings per channel off Min Typ 38 Max Units mW CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Electrical Characteristics - CDK8307E (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted) Symbol Performance SNR SINAD SFDR HD2 HD3 ENOB Crosstalk Parameter Conditions FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz FIN = 8MHz FIN = 30MHz See note (1) on page 13 Min 68.5 68 74 85 75 Typ 70.1 70 69.6 69.5 77 76 90 90 77 76 11.3 11.3 95 173 Max Units dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc bits bits dBc mA mA mW mW mW W mW mW mW MSPS Signal to Noise Ratio Signal to Noise and Distortion Ratio Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits Power Supply Analog supply current Digital supply current Analog power Dissipation Digital power Dissipation Total power Dissipation Power Down Dissipation Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Power down mode Deep sleep mode All channels. in sleep ch. mode (light sleep) Power dissipation savings per channel off 80 40 Digital and output driver supply 88 312 158 470 10 56 116 44 Clock Inputs Maximum Conversion Rate Minimum Conversion Rate MSPS Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted) Symbol Clock Inputs Duty Cycle Compliance Input range, differential Input range, sine Input range, CMOS Input common mode voltage Input capacitance Differential input swing Differential input swing, sine wave clock input CLKN connected to ground Keep voltages within gnd and voltage of OVDD Differential 0.3 2 20 200 800 VOVDD VOVDD -0.3 80 %high mVpp mVpp mVpp V pF CMOS, LVDS, LVPECL Parameter Conditions Min Typ Max Units Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 13 Data Sheet Symbol Parameter Conditions VOVDD 3.0V VOVDD = 1.7V - 3.0V VOVDD 3.0V VOVDD = 1.7V - 3.0V Min 2 0.8 * VOVDD 0 0 Typ Max Units V V Logic Inputs (CMOS) VIH VIL IIH IIL CI High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Input Capacitance Compliance VOUT VCM Differential Output Voltage Output Common Mode Voltage Output Coding Default/Optional 350 1.2 Offset Binary/2`s Complement 0.8 <0.5 Start up time from Power Down to Active Mode. References have reached 99% of final value. (See section Clock Frequency) Start up time from Sleep Mode to Active Mode 260 15 0.5 1 14 Excluding programmable phase shift 7 +2.6 45 * TLVDS 0.8 0.2 * VOVDD 10 10 3 LVDS V CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS V A A pF Data Outputs (LVDS) mV V Timing Characteristics TAP Aperture Delay Aperture Jitter ns ps 992 clock cycles s s clk cycles clk cycles ps 7 +4.2 55 2.5 Calculated from 20% to 80% Calculated from 20% to 80% 0.4 0.4 * TLVDS RMS TPD TSLP TOVR TLAT tdata tPROP Start up Time from Power Down Startup Time from Sleep Out Of Range Recovery Time Pipeline Delay LCLK to Data Delay Time Clock Propogation Delay LVDS Bit-Clock Duty-Cycle Frame clock cycle-to-cycle jitter LVDS Output Timing Characterisctics 250 7 +3.5 * TLVDS ns % LCLK cycle % LCLK cycle ns ns TEDGE TCLKEDGE Note: Data Rise- and Fall Time Clock Rise- and Fall Time (1) Signal applied to 7 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz (2) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet LVDS Timing Diagrams Analog Input CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS ADC Clock TLVDS LCLKP LCLKN FCLKN FCLKP Dxx<1:0> D10 N-2 D11 N-2 D0 N-1 D1 N-1 D2 N-1 D3 N-1 D4 N-1 D5 N-1 D6 N-1 D7 N-1 D8 N-1 D9 N-1 D10 N-1 D11 N-1 D0 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N D9 N D10 N TPROP Figure 1. 12-bit Output, DDR Mode Analog Input ADC Clock LCLKP LCLKN FCLKN FCLKP Dxx<1:0> D0 N-1 D1 N-1 D2 N-1 D3 N-1 D4 N-1 D5 N-1 D6 N-1 D7 N-1 TLVDS D8 N-1 D9 D10 D11 D12 D13 N-1 N-1 N-1 N-1 N-1 D0 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N D9 N D10 D11 D12 D13 N N N N TPROP Figure 2. 14-bit Output, DDR Mode Analog Input ADC Clock LCLKP LCLKN FCLKN FCLKP Dxx<1:0> TLVDS D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 N-2 N-2 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 D0 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N D9 N D10 N TPROP Figure 3. 12-bit Output, SDR Mode TLVDS LCLKP LCLKN Dxx<1:0> TLVDS/2 Rev 1A tdata Figure 4. Data Timing 15 (c)2009 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Serial Interface The CDK8307 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low: n n n Serial data are shifted into the chip CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS At every rising edge of SCLK, the value present at SDATA is latched SDATA is loaded into the register every 24th rising edge of SCLK Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is divided into two parts: n n The first eight bits form the register address The remaining 16 bits form the register data Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. Timing Diagram Figure 5 shows the timing of the serial port interface. Table 1 explains the timing variables used in the Timing Diagram. tcs CSN SCLK SDATA A7 A6 A5 tlo thi tclk th ts tch tch chi i A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. Serial Port Interface Timing Diagram Table 1. Serial Port Interface Timing Definitions Parameter tcs tch thi tlo tclk ts th Description Setup time between CSN and SCLK Hold time between CSN and SCLK SCLK high time SCLK low time SCLK period Data setup time Data hold time Minimum Value 8 8 20 20 50 5 5 Unit ns ns ns ns ns ns ns Register Initialization Before CDK8307 can be used, the internal registers must be initialized to their default values and power down must be activated. This can be done immediately after applying supply voltage to the circuit. Register initialization can be done in one of two ways: 1. By applying a low-going pulse (minimum 20ns) on the RESETN pin (asynchronous). 2. By using the serial interface to set the RST bit high. Internal registers are reset to default values when this bit is set. The RST bit is self-reset to zero. When using this method, do not apply any low-going pulse on the RESETN pin. Power down initialization can be done in one of two ways: 1. By applying a high-going pulse (minimum 20ns) on the PD pin (asynchronous). 2. By cycling the SPI register 0Fhex PD bit to high (reg value '0200'hex) and then low (reg value '0000'hex). Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 16 Data Sheet Serial Register Map Table 2. Summary of Functions Supported by the Serial Interface Name rst pd_ch<8:1> sleep pd pd_pin_cfg<1:0> Description Software reset. This bit is self-clearing Channel-specific power-down Go to sleep-mode Go to power-down Configures the PD pin for sleep-modes LVDS current drive programmability for LCLKP and LCLKN pins LVDS current drive programmability for FCLKP and FCLKN pins LVDS current drive programmability for output data pins Enables internal termination for LVDS buffers Programmable termination for LCLKN and LCLKP buffers Programmable termination for FCLKN and FCLKP buffers Programmable termination for output data buffers Swaps the polarity of the analog input pins electrically Enables a repeating full-scale ramp pattern on the outputs Enable the mode wherein the output toggles between two defined codes Default Inactive Inactive Inactive Inactive PD pin configured for power-down mode 3.5mA drive 3.5mA drive 3.5mA drive Termination disabled Termination disabled Termination disabled Termination disabled IPx is positive input Inactive Inactive X 1 1 1 X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X 0 X 0 X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS X X 00 0F ilvds_lclk<2:0> ilvds_ frame<2:0> ilvds_dat<2:0> en_lvds_term term_lclk<2:0> term_ frame<2:0> term_dat<2:0> invert_ch<8:1> en_ramp dual_custom_pat single_custom_ pat bits_custom1<13:0> bits_custom2<13:0> gain_ch1<3:0> gain_ch2<3:0> gain_ch3<3:0> gain_ch4<3:0> gain_ch5<3:0> gain_ch6<3:0> gain_ch7<3:0> gain_ch8<3:0> X X X 11 12 24 25 Enables the mode wherein the Inactive output is a constant specified code Bits for the single custom pattern and for the first code of the dual Inactive custom pattern. <0> is the LSB Bits for the second code of the dual custom pattern Inactive 26 27 Programmable gain for channel 1 0dB gain Programmable gain for channel 2 0dB gain Programmable gain for channel 3 0dB gain Programmable gain for channel 4 0dB gain Programmable gain for channel 5 0dB gain Programmable gain for channel 6 0dB gain Programmable gain for channel 7 0dB gain Programmable gain for channel 8 0dB gain 2A Rev 1A 2B (c)2009 CADEKA Microcircuits LLC www.cadeka.com 17 Data Sheet Table 2. Summary of Functions Supported by the Serial Interface (Continued) Name phase_ddr<1:0> pat_deskew pat_sync btc_mode msb_first en_sdr Description Controls the phase of LCLK output relative to data Enable deskew pattern mode Enable sync pattern mode Binary two's complement format for ADC output data Serialized ADC output data comes out with MSB first Enable SDR output mode. LCLK becomes a 12x input clock Default 90 degrees Inactive Inactive Straight offset binary LSB-first output DDR output mode X X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 42 X X 0 X X 0 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS 45 46 fall_sdr Rising edge Controls whether the LCLK risof LCLK ing or falling edge comes in the comes in the middle of the data window when middle of the operating in SDR mode data window Nominal X 1 perfm_cntrl<2:0> ADC performance control lvds_pd_mode lvds_num_bits lvds_advance lvds_delay fs_cntrl<5:0> clk_freq<1:0> X X X X X X ext_vcm_bc<1:0> VCM buffer driving strength control Nominal Controls LVDS power down mode High z mode Sets the number of LVDS output bits Advance LVDS data bits and frame clock by one clock cycle Delay LVDS data bits and frame clock by one clock cycle Fine adjust ADC full scale range Input clock frequency 12-bit Inactive Inactive 0% change 65MHz 50 52 X 0 X X X 0 X X X X X X X 53 55 56 Description of Serial Registers Table 3. Software Reset Name rst Description Self-clearing software reset Default Inactive D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 00 X Setting the rst register bit to '1', resets all internal registers including the rst register bit itself. Table 4. Power-Down Modes Name pd_ch<8:1> sleep pd pd_pin_cfg<1:0> lvds_pd_mode Description Channel-specific power-down Go to sleep-mode Go to power-down Configures the PD pin for sleep-mode Default Inactive Inactive Inactive PD pin configured for powerdown mode X X X X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex X X X X X X X X 0F Rev 1A Controls LVDS power down mode High z mode 52 (c)2009 CADEKA Microcircuits LLC www.cadeka.com 18 Data Sheet Setting pd_ch Name ilvds_lclk<2:0> ilvds_ frame<2:0> ilvds_dat<2:0> Description LVDS current drive programmability for LCLKP and LCLKN pins. LVDS current drive programmability for FCLKP and FCLKN pins. LVDS current drive programmability for output data pins. Default 3.5mA drive 3.5mA drive 3.5mA drive X X X X X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Address In Hex X X X 11 The current delivered by the LVDS output drivers can be configured as shown in Table 6. The default current is 3.5mA, which is what the LVDS standard specifies. Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and LCLKN pins. Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and FCLKN pins. Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1] N pins. Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data ilvds_*<2:0> 000 001 010 011 100 101 110 111 LVDS Drive Strength 3.5 mA (default) 2.5 mA 1.5 mA 0.5 mA 7.5 mA 6.5 mA 5.5 mA 4.5 mA Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 19 Data Sheet Table 7. LVDS Internal Termination Programmability Name en_lvds_term term_lclk<2:0> term_ frame<2:0> term_dat<2:0> Description Enables internal termination for LVDS buffers Programmable termination for LCLKN and LCLKP buffers Programmable termination for FCLKN and FCLKP buffers Programmable termination for DxP and DxN buffers Default Termination disabled Termination disabled Termination disabled Termination disabled D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex X CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS 1 1 1 X X X X X X X X X 12 The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal termination mode can be selected by setting the en_lvds_term bit to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table 8 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can vary by up to 20% from device to device and across temperature. Table 8. LVDS Output INternal Termination for LCLK, FCLK, and Data term_*<2:0> 000 001 010 011 100 101 110 111 LVDS Internal Termination Termination Disabled 280 165 100 125 82 67 56 Table 9. Analog Input Invert Name invert_ch<8:1> Description Swaps the polarity of the analog input pins electrically Default IPx is positive input D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 24 X X X X X X X X The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting the bits marked invert_ch <8:1> (individual control for each channel) causes the inputs to be swapped. INx would then represent the positive input, and IPx the negative input. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 20 Data Sheet Table 10. LVDS Test Patterns Name en_ramp dual_custom_pat single_custom_ pat bits_custom1<13:0> bits_custom2<13:0> pat_deskew pat_sync Description Enables a repeating full-scale ramp pattern on the outputs Default Inactive D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex X 0 0 X X X X X X X X X X 0 X 0 X 0 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Enable the mode wherein the output Inactive toggles between two defined codes Enables the mode wherein the Inactive output is a constant specified code Bits for the single custom pattern Inactive and for the first code of the dual custom pattern. <0> is the LSB Bits for the second code of the dual custom pattern Enable deskew pattern mode Enable sync pattern mode Inactive Inactive Inactive 0 X X X X 25 26 X X X X X X X X X X X X X X 0 X X 0 27 45 To ease the LVDS synchronization setup of CDK8307, several test patterns can be set up on the outputs. Normal ADC data are replaced by the test pattern in these modes. Setting en_ramp to '1' sets up a repeating full-scale ramp pattern on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and starts the ramp again after reaching the full-scale code. A constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value in bits_custom1<13:0>. In this mode, bits_custom1<13:0> replaces the ADC data at the output, and is controlled by LSB-first and MSB-first modes in the same way as normal ADC data are. The device may also be made to alternate between two codes by programming dual_custom_pat to '1'. The two codes are the contents of bits_custom1<13:0> and bits_custom2<13:0>. Two preset patterns can also be selected: 1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with '01010101010101' (two LSBs removed in 12 bit mode). 2. Sync pattern: Set using pat_sync, the normal ADC word is replaced by a fixed 1111110000000 word. Note: Only one of the above patterns should be selected at the same time. Table 11. Programmable Gain Name gain_ch1<3:0> gain_ch2<3:0> gain_ch3<3:0> gain_ch4<3:0> gain_ch5<3:0> gain_ch6<3:0> gain_ch7<3:0> gain_ch8<3:0> Description Default D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex Programmable gain for channel 1 0dB gain Programmable gain for channel 2 0dB gain Programmable gain for channel 3 0dB gain Programmable gain for channel 4 0dB gain Programmable gain for channel 5 0dB gain Programmable gain for channel 6 0dB gain Programmable gain for channel 7 0dB gain Programmable gain for channel 8 0dB gain X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2A 2B X X X X Rev 1A CDK8307 includes a purely digital programmable gain option in addition to the Full-scale Control. The programmable gain of each channel can be individually set using a set of four bits, indicated as gain_chn<3:0> for Channel x. The gain setting is coded in binary from 0dB to 12dB, as shown in Table 12 on the following page. (c)2009 CADEKA Microcircuits LLC www.cadeka.com 21 Data Sheet Table 12. Gain Setting for Channels 1-8 gain_chx<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Channel x Gain Setting 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB Do not use Do not use Do not use CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Table 13. LVDS Clock Programmability and Data Output Modes Name phase_ddr<1:0> btc_mode msb_first en_sdr Description Controls the phase of LCLK output relative to data Binary two's complement format for ADC output data Serialized ADC output data comes out with MSB first Enable SDR output mode. LCLK becomes a 12x input clock Default 90 degrees Straight offset binary LSB-first output DDR output mode X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 42 X X X 46 fall_sdr Rising edge Controls whether the LCLK risof LCLK ing or falling edge comes in the comes in the middle of the data window when middle of the operating in SDR mode data window X 1 The output interface of CDK8307 is normally a DDR interface, with the LCLK rising and falling edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data using bits phase_ddr<1:0>. The LCLK phase modes are shown in Figure 6. The default timing is identical to setting phase_ddr<1:0> = '10'. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 22 Data Sheet PHASE_DDR<1:0>='00' = 270 FCLKN FCLKP LCLKP LCLKN Dxx<1:0> PHASE_DDR<1:0>='10' = 90 (Default) FCLKN FCLKP LCLKN LCLKP Dxx<1:0> PHASE_DDR<1:0>='01' =180 FCLKN FCLKP LCLKN LCLKP Dxx<1:0> PHASE_DDR<1:0>='11' = 0 FCLKN FCLKP LCLKP LCLKN Dxx<1:0> CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Figure 6. Phase Programmability Modes for LCLK The device can also be made to operate in SDR mode by setting the en_sdr bit to '1'. The bit clock (LCLK) is output at 12x times the input clock in this mode, two times the rate in DDR mode. Depending on the state of fall_sdr, LCLK may be output in either of the two manners shown in Figure 7. As can be seen in Figure 7, only the LCLK rising (or falling) edge is used to capture the output data in SDR mode. The SDR mode is not recommended beyond 40MSPS because the LCLK frequency becomes very high. EN_SDR='1', FALL_SDR_'0' FCLKN FCLKP LCLKP LCLKN Dxx<1:0> EN_SDR='1', FALL_SDR_'1' FCLKN FCLKP LCLKN LCLKP Dxx<1:0> Figure 7. SDR Interface Modes The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to '1' which inverts the MSB. The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Programming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge. Table 14. Number of Serial Output Bits Name lvds_num_bits lvds_advance lvds_delay Description Default D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex Sets the number if LVDS output bits 12-bit Advance LVDS data bits and frame clock by one clock cycle Delay LVDS data bits and frame clock by one clock cycle Inactive Inactive 0 X X 0 X 53 Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 23 Data Sheet The ADC channels have 13 bits of resolution. There are two options for the serial LVDS outputs, 12 bits or 14 bits, selected by setting lvds_num_bits to '0' or '1', respectively. In 12-bit mode, the LSB bit from the ADCs are removed in the output stream. In 14-bit mode, a '0' is added in the LSB position. Power down mode must be activated after or during a change in the number of output bits. To ease timing in the receiver when using multiple ADC chips, the CDK8307 has the option to adjust the timing of the output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS clock cycle forward or backward, by using lvds_advance and lvds_delay, respectively. See figure 8 for details. Note that LCLK is not affected by lvds_delay or lvds_advance settings. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS TLVDS LCLKP LCLKN TPROP default: FCLKP FCLKN Dxx<1:0> D3 D4 D5 D6 D7 D8 D9 D10 D11 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 D0 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N D9 N TPROP lvds_delay = `1': FCLKP FCLKN Dxx<1:0> D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 TLVDS D0 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N TPROP lvds_advance = `1': FCLKP FCLKN Dxx<1:0> D4 D5 D6 D7 D8 D9 D10 D11 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 *LVDS output timing adjustment D0 N TLVDS D1 N D2 N D3 N D4 N D5 N D6 N D7 N D8 N D9 N D10 N Figure 8: LVDS Output Timing Adjustment Table 15. Full Scale Control Name fs_cntrl<5:0> Description Fine adjust ADC full scale range Default 0% change D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 55 X X X X X X The full-scale voltage range of CDK8307 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register. Changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. This leads to a maximum range of 10% adjustment. Table 16 shows how the register settings correspond to the full-scale range. Note that the values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous. The full-scale control and the programmable gain features differ in two major ways: 1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. The programmable gain feature has much coarser gain steps and larger range than the full-scale control. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 24 Data Sheet Table 16. Register Values with Corresponding Change in Full-Scale Range fs_cntrl <5:0> 111111 ... 100001 100000 011111 ... 000000 Full-Scale Range Adjustment +9.7% ... +0.3% +0% -0.3% ... -10% CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Table 17. Clock Frequency Name clk_freq<1:0> Description Input clock frequency Default 50 - 80MHz D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex 56 X X To optimize startup time a register is provided where the input clock frequency can be set. Some internal circuitry has startup times that are frequency independent. Default counter values are set to accommodate these startup times at the maximum clock frequency. This will lead to increased startup times at low clock frequency. Setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual startup time, such that the startup time will be reduced. The start up times from Power Down mode and Deep Sleep mode are changed by this register setting. Table 18. Clock Frequency Settings clk_freq <1:0> 00 01 10 11 Clock Frequency (MHz) 50 - 80 32.5 - 50 20 - 32.5 15 - 20 Startup Delay (clock cycles) 992 640 420 260 Startup Delay (s) 12.4 - 19.8 12.8 - 19.7 12.9 - 21 13 - 17.3 Table 19. Performance Control Name perfm_ cntrl<2:0> ext_vcm_ bc<1:0> Description ADC performance control VCM buffer driving strength control Default Nominal Nominal X X D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Address In Hex X X X 50 There are two registers that impact performance and power dissipation. The perfm_cntrl register adjusts the performance level of the ADC core. If full performance is required, the nominal setting must be used. The lowest code can be used in situations where power dissipation is critical and performance is less important. For most conditions the performance at the minimum setting will be similar to nominal setting. However, only 10-bit performance can be expected at worst case conditions. The power dissipation savings shown in Table 20 are only approximate numbers for the ADC current alone. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 25 Data Sheet Table 20. Performance Control Settings performance_control <2:0> 100 101 110 111 000 (default) 001 010 011 Power Dissipation -40% (lower performance) -30% -20% -10% Nominal Do not use Do not use Do not use CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is not in use, the buffer can be switched off. If current is drawn from the VCM pin, the driving strength can be increased to keep the voltage on this pin at the correct level. Table 21. External Common Mode Voltage Buffer Driving Strength ext_vcm_bc <1:0> 00 01 (default) 10 11 VCM Buffer Driving Strength Off (VCM floating) Low High Max Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 26 Data Sheet Therory of Operation The CDK8307 is an 8-channel, high-speed, CMOS ADC. The 13-bits given out by each channel are serialized to 12, 13 or 14-bits and sent out on a single pair of pins in LVDS format. All eight channels of the CDK8307 operate from a single differential or single ended clock. The sampling clocks for each of the eight channels are generated from the clock input using a carefully matched clock buffer tree. The 12x/13x/14x clock required for the serializer is generated internally from FCLK using a phase-locked loop (PLL). A 6x/6.5x/7x and 1x clock are also output in LVDS format, along with the data to enable easy data capture. The CDK8307 uses internally generated references that can be shorted across several devices to improve gain-matching. The differential reference value is 1V. This results in a differential input of -1V to correspond to the zero code of the ADC, and a differential input of +1V to correspond to the full-scale code (code 8191). The ADC employs a pipelined converter architecture. Each stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at 13-bit level. The CDK8307 operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by DVDD and DVSS. differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Figure 9. Input Configuration Diagram DC-Coupling Figure 10 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as a reference to set the common mode voltage. The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the CDK8307 input specifications. Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in Figure 10 must be varied according to the recommendations for the driver. Recommended Usage Analog Input The analog input to the CDK8307 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The VCM pin provides a voltage suitable as common mode voltage reference. The internal buffer for the VCM voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_ bc<1:0> register. Figure 9 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small 43 33pF 43 Rev 1A Figure 10. DC-Coupled Input (c)2009 CADEKA Microcircuits LLC www.cadeka.com 27 Data Sheet AC-Coupling A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 11 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to keep phase mismatch between the differential ADC inputs small for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS pF Figure 12. AC-Coupled Input Note that startup time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kick-backs from the ADC not are effectively terminated at the signal source, the input network of Figure 13 can be used. The configuration is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. 33 RT 47 33 Figure 11. Transformer Coupled Input If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in Figure 10 can be used. Figure 12 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. 1:1 120nH 33 optional RT 68 120nH 220 pF 33 Figure 13: Alternative Input Network Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. This capacitor attenuate the ADC kick-back even more, and minimize the kicks traveling towards the source. However the impedance match seen into the transformer becomes worse. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 28 Data Sheet Clock Input and Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK8307 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, and hence a wide common mode voltage range is accepted. Differential clock sources as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least 0.8Vpp. The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation below. SNRjitter = 20 * log (2 * For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input. CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS * FIN * t) where FIN is the signal frequency, and t is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 29 Data Sheet Mechanical Dimensions QFN-64 aaa C A A D D1 aaa C B ccc C A A2 A3 A1 Symbol A A1 A2 A3 b D D1 D2 E E1 E2 F G L e Min - 0.00 - 0.008 Inches Millimeters Typ Max Min Typ - 0.035 - - 0.0004 0.002 0.00 0.01 0.026 0.028 - 0.65 0.008 REF 0.2 REF 0.010 0.012 0.2 0.25 0.354 BSC 9.00 BSC 0.354 BSC 8.75 BSC 0.205 0.213 5.0 5.2 0.354 BSC 9.00 BSC 0.344 BSC 8.75 BSC 0.205 0.213 5.0 5.2 - - 1.3 - 0.0168 0.024 0.24 0.42 0.016 0.020 0.3 0.4 0.020 BSC 0.50 BSC - 12 0 - Tolerance of Form and Position 0.10 0.004 0.10 0.004 0.05 0.002 Max 0.9 0.05 0.7 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS 0.30 0.197 5.4 0.197 0.05 0.0096 0.012 0 5.4 - 0.6 0.5 12 E E1 1 aaa bbb ccc Pin 1 ID 0.05 Dia. 1 bbb C A C seating plane NOTES: 1. All dimensions are in millimeters. 2. Die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. Dimensioning & tolerances conform to ASME y14.5m. -1994. 4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max 0.08mm. 8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring. 9. Applied only to terminals. 10. Package corners unless otherwise specipied are r0.1750.025mm. bbb C B B 1.14 1.14 TOP VIEW Pin 1 ID Dia. 0.20 0.45 D2 F SIDE VIEW G E2 L e b 0.10 M C A B L BOTTOM VIEW Rev 1A (c)2009 CADEKA Microcircuits LLC www.cadeka.com 30 Data Sheet Mechanical Dimensions (Continued) TQFP-80 TQFP-80 Symbol A A1 A2 A3 b c D E e HD HE L Lp L1 x y ZD ZE Dimensions (mm) 1.20 0.10 0.05 1.00 0.05 0.25 0.22 0.05 0.145 +0.055 0.145 -0.045 12.00 0.20 12.00 0.20 0.50 14.00 0.20 14.00 0.20 0.50 0.60 0.15 1.00 0.20 0.08 0.08 1.25 1.25 3 +5 3 -3 CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS NOTE: Each lead centerline is located within 0.08mm of its true position at maximum material condition. Detail of Lead End For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2009 by CADEKA Microcircuits LLC. All rights reserved. Rev 1A A m p l i fy t h e H u m a n E x p e r i e n c e |
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